Split-gate non-volatile Flash memory cells having a select gate, a floating gate, a control gate and an erase gate are well known in the art. See for example U.S. Pat. Nos. 6,747,310, 7,868,375 and 7,927,994, and published application 2011/0127599, which are all incorporated herein by reference in their entirety for all purposes. Such split-gate memory cells include a channel region in the substrate that extends between the source and drain. The channel region has a first portion underneath the floating gate (hereinafter called the FG channel, the conductivity of which is controlled by the floating gate), and a second portion underneath the select gate (hereinafter the “WL channel” (wordline), the conductivity of which is controlled by the select gate).
In order to increase performance and reduce operating voltages for read, program and erase, various insulation and other thicknesses can be optimized. However, there is a need for further cell optimization not achievable by cell geometry optimization alone.